This invention relates to a buffer memory system for use in a data processing system. The data processing system may be what is called a digital electronic computer system.
In general, a computer system comprises a central processor and a main memory. Programs and data for use in data processing, are stored in the main memory as entries or contents thereof. For an increased number of entries, the main memory must have a large memory capacity. Among others, the time required to access the main memory becomes longer.
In order to shorten the access time and thereby to raise the speed of data processing, a buffer memory of a smaller memory capacity is used in storing information of a greater frequency of use. The information is given by copies of the entries in the main memory. The central processor directly accesses the buffer memory at first for desired entries. Only when the desired entries are not found in the buffer memory, the central processor accesses the main memory and stores the accessed entries in the buffer memory.
The programs are often fragmented into a plurality of program blocks. Transfer of the program blocks or movement of blocks of information between the main and the buffer memories, is called "paging" in the art.
When the art of paging in resorted to, it is unnecessary for each user of the computer system to direct attention to the relation between the memory capacity of the main memory and the length of the program for the user and to the manner of fragmentation of the program. A physical (real) address is automatically derived from a logical (virtual) address specified by the programmer for the program.
With the concept of logical addresses in mind, a translation storage system is disclosed by David W. Anderson et al, assignors to International Business Machines Corporation, in a United States patent application filed June 30, 1971, and matured into U.S. Pat. No. 3,761,881. The Anderson et al system comprises a buffer memory, a translation look aside table for retaining current logical-to-physical address translations, and a buffer directory for accessing the buffer memory with physical addresses. Each logical address comprises a virtual portion and a real displacement which is common to a physical address and is representative of an address in a page of the buffer memory. Although the Anderson et al system has worked admirably, the number of addresses in a page is restricted and can be increased only by an increase in the bulkiness of hardware.
An improved memory system is revealed by Joseph A. Alvarez et al, assignors to International Business Machines Corporation, in a United States patent application filed Jan. 20, 1972, and issued as U.S. Pat. No. 3,723,976. According to Alvarez et al, each of a plurality of buffer memories in a memory system is accompanied by a fetch directory or control table and a broadcast store directory or auxiliary directory. The control table is for accessing the accompanying buffer memory at first. When the requested information is not found in the accompanying buffer memory, the control table accesses the auxiliary directories. The Alvarez et al system is excellent in avoiding the bulkiness of hardware. The system is, however, still defective in that the requested information is obtained from the buffer memories in two ways, one directly from the accompanying one and the other from one of the other buffer memories. The access time therefore increases when the information is present in one of the other buffer memories. Furthermore, complicated control for the two ways, is unavoidable.